Tuesday, 20 January 2015

DFT Engineer - Interview Questions 2

Following are the Interview Questions for the Post of DFT Engineer. The questions are collected from my friends, who attended the interviews and Some of them are from the interviews that I've attended.

  • EDTbypass is passing. EDT chain patterns are failing. What could be the reasons?
  • (lockup latches not present between edtclock, shiftclock.)
  • Two subchips are there. Shifting power is huge. HOw to reduce power dissipation?
  • What are the options you have, without affecting coverage and test time? (HW or SW options)
  • Setup vioations are there in your design. Which patterns would fail? (s@ or @speed?)
  • Hold vioations are there. Which patterns would fail?
  • -ve, +ve flops are connected, +ve, -ve flops are connected without lockup latch. 
  • Which one is better in terms of setup and hold timing?
  • Why do we need a lockup latch at all? what happens if we dont use it?
  • Two flops will have the same values during shift. Whats the effect of it?
  • JTAG : how do you connect tdi, tdo, tms, trst, from board level TAP to all chips on the board.
  • explain an algorithm for MBIST.
  • Where do we use parallel testbench? Whats the use of parallel simulations?
  • TEstpoint? why do we need them?
  • If you have simulations failures, what are the things you would look at?
  • (setup, libs, clocks, what else?)
  • In synthesis, if area is not meeting the target, what would you do?
  • If some flops in two clock domains are failing, (S@ patterns), and those failures are expected.
  • HOw would you make them pass them on silicon? (no design changes are allowed.)
  • Atspeed coverage is always less than STUCK-at coverage. Why?
  • P1500? are you aware of it?
  • AND gate - optimal input pattern set to detect all S@ faults.
  • how to swap two numbers in C (using a single line of code)
  • 2**300, 3**200 - which one is bigger?
  • explain EDT logic.
  • Simulation mismatches you have seen. how did you debug?
  • LOC - LOS adv and disadv.
  • What is the significance of DFT?
  • why atspeed coverage is low than S@ coverage?
  • why is target coverage 90% at intel? and 99% at marvell?
  • What is that hindering you from achieving more coverage?
  • what are the issues you've faced in pattern simulations?
  • What is the need to do Timing simulations of ATPG patterns, even after the timing is analysed completely?
  • What is needed between two power domains, in the DFT perspective? (level shifters?)
  • Two different clock domains are there. How do you target the at-speed faults?
  • How do you improve fault coverage?
  • What are the issues you've seen in simulations? (design bugs)
  • Why do we need OCC?
  • Why do we need EDT?
  • How do you test multicycle paths at-speed?
  • What happens if you don't specify any NCPs?
  • What are EDT aborted faults?

DFT Engineer - Interview Questions 1

Following are the Interview Questions for the Post of DFT Engineer. The questions are collected from my friends, who attended the interviews and Some of them are from the interviews that I've attended.
  • What is LSSD and Mux-DFF?
  • Draw a logic ciruit to detect a rising edge in an input signal.
  • Explain how scan works.
  • What are Launch Off Capture,  Launch Off Shift  ?
  • What are mealey and moore state machines? advantages and disadvantages.
  • Explain boundary scan and tap controller.
  • Design rule checks in ATPG (SCAN DRCs)
  • Mismatch debug in ATPG.
  • What is EDT logic and how does it work?
  • How do the chains connect in EDTbypass mode? Compression ratio?
  • How does the tester time reduce in EDT?
  • Can you put just 1 flop in EDT mode chains and reduce the tester time to just 1 shift??
  • Patterns count increases if chain length is reduced. Y??
  • What is LOC, LOS? How do they work? Waveforms??
  • What is DFT ? what are its adv and disadv?
  • Why delay increases if u use mux DFF?
  • What happens to setup time of the DFF in Mux DFF??
  • Some comb logic is given.. is that fully controllable and observable ??
  • Some Sequential ckt..  Controllable and observable ?? what do you do to make it become so??
  • Parallel pattern mismatches? How did u debug?
  • Lock up latch use?
  • Positive and negative edge triggered flops.. how will u connect in a chain?
  • Explain EDT logic. Decompressor, Compactor.
  • Masking logic, Mask shift and hold regs.
  • Compression ratio, EDT control signals – EDT update, EDT clock
  • Fault aliasing, Masking bits generation – coverage effects.
  • 2x1 MUX using NAND gates.
  • Generate a Clock div by 2, with 25% duty cycle.
  • To detect a fault in a circuit, what are the input test vectors to be given?
  • All Test Patterns for an 2-input AND gate (optimal set).
  • Sequence detector, whole circuit. 
  • Setup time, Hold time problems.
  • LOC, LOS differences. 
  • Scan chain diagnosis – serial pattern failing on Silicon, How do you detect?
  • ATPG DRC violations?
  • Simulation mismatches debug.  
  • JTAG – Instructions – intest, extest, preload/sample.
  • LOC, LOS – main difference.
  • Scan chain connections, mux-DFF. (How is a scan chain is connected?)

Monday, 19 January 2015

RTL Verification Engineer - Interview Questions

Following are the Interview Questions for the Post of RTL Verification Engineer, at a Top semiconductor product based company in Bengaluru.
I don't remember few questions in the written test. Please don't mind.

WRITTEN TEST - 20 QUESTIONS (8 Digital, 6 Verilog and 6 Aptitude) - 45 MIN.

 1. draw a circuit to divide a clock by 2.
 2. draw a circuit to multiply a clock with 2.
 3. draw a state diagram for sequence detector for 1011
 4. draw a logic circuit for Y = X*X where X is a 2 bit input.
 5. draw a logic circuit +ve level sensitive latch using 2:1 MUX
 6. draw a logic circuit for a -ve edge triggered flipflop using 2:1 MUXes
 7. design a mod-5 counter.
 8. calculate the max. frequency of operation. (CLK-Q delay, combinational logic delay, setup and hold times are given.)

 1. write the verilog code for the state machine above.
 2. question on different delay assignment statements in verilog.. draw the waveforms.
 3. if(a) if(a=1) if(a==1) if(a===1) .. if a is X, what will be the output. which part of the if-else case is executed?
 4. question on parameter, defparameter.. what is a parameter is defined again? overridden?
 5. question on execution on blocking and non-blocking statements.

 1. 25 horses are there. only 5 can be put in race at once. what is the min. nmbr of races to decide the fastest horse?
 2. average of 5 nmbrs starting from m is n. avg of 9 nmbrs starting from m+2 is ?



 Explain CMOS inverter operation.
 Design all basic gates using 2:1 MUX.
 Design a counter which counts a sequence of 1, 3,5 and 7. minimum number of flops required for this?
 CMOS inverter has delay of 2ns. An input pulse of width less than 2ns is give. will is pass through the gate?
 what is logical effort? explain logical effort calculation for a CMOS inverter and other gates (XOR, XNOR)?
 what are asynchronous and synchronous reset? which is better ? why?
 design a priority encoder(8x3). where do you use it?
 The delay of circuit depends on ? critical path, setup time.
 what are adv and disadv of  mealey and moore machines?
 What is event queue ?
 What happens in a CMOS inverter when PMOS and NMOS are interchanged?
 In CMOS inverter, vdd=5v, vss=0v, Vthp=vthn=1.8V, input = 1.8v is given. what will be the output?


Synchronize the below pulse with the clock and reduce its width to one clock period.
 ______|                     |___________ ( here the pulse width is more than 3 clock periods )

 Net delay and gate delay assignments in verilog?
 Blocking and non-blocking statements and where they are used? 
 Explain the MOS transistor operation.
 Setup time and hold times of a flop and a latch?
 CLK-Q delay in a flop and D-Q delay of a latch.

 12,6,6,3,6,9,18,45, ?? what is the next number?
 A question on faces of a dice?
 8 balls are there. 1 defective ball is present in them. you have a weighing balance. 
 using only 2 times , how will you find out the defective ball?
 How will you create 4 equilateral triangles using 6 match sticks?
 what is the angle between hours and minutes hand at 8:10 ?
  draw a ckt to increase the pulse width to 3 periods.
 XOR gate is there. output is fedback to 1 input. what will be the output?
 A person had 17 cows. How to share them between his 3 sons in fractions of 1/2, 1/3, 1/9th of total respectively. (There is nothing wrong in this question)

Physical Design Engineer - Interview Questions

Following are the Interview Questions for the Post of Physical Design Engineer. The questions are collected from my friends, who attended the interviews.

Given a circuit, what is the minimum time period of the clock so that the circuit can function properly?
What are the worst case and best case scenarios for timing analysis? (PVT corners)
What are the PVT variations? Why do they occur in the Silicon?
Explain Temperature inversion?
Why do we do timing sign-off at -10 degrees temperature, even though after Power-up, the chip temperature increases above the room temperature? 
What happens immediately after you Power-up the chip?
Difference between a latch and flip-flop?
Draw a flip-flop using two latches. Explain using waveforms.
Why do we use a lock-up latch in DFT ? Explain using waveforms.

Given a circuit, explain how you do setup and hold checks.
If there are any hold violations, what would you do?
IF there are any setup violations, what would you do?
For which case, you consider minimum delays, and for which case, you would consider max delays?
What are the min,typ,max delays specified in a timing library?
What are all the factors that the Cell delay depend on?
If we have setup violations, we do clock-pushing(skewing the capture clock-edge). Would you do clock-pushing for all the flops in your design? (if all flops have setup violations) If no, Why?
Given a ckt., what all data would you need to do STA? 
What info would be there in the Timing libs in STA/synthesis ?
Does the Clock-Q of a flop depends on transition of D input ?
Does the setup time vary for a flop?
A train of length 100m is running a speed of 60KMPH. How much time does it take to pass a platform of length 1KM?

Explain the steps in synthesis in detail.
What is incremental synthesis?
What is the info present in .lib files?
How does the load capacitance and transition time effect the delay?
What if a load cap or trns time exceeds the values in .lib? How does the tool handle it?
What would you do to reduce transition time ? 
Given a circuit, find the maximum operating frequency.
Will hold violation be there if you increase the frequency? Why?
What are the different corners for which you did STA?
Why do you do STA at two corners for slow process? (slow125, slown10)
What is Cbest/worst, RCbest/worst?
How does clock skew effect the timing?
What are on-chip variations? How do you take care of them ?
What is clock uncertainty? 
Given a ckt., tell what delays (min, typ, max) will you consider at different places(data path, clock path) for setup checks, and for hold checks. Why ?
How does an inverter work if the PMOS and NMOS are switched?

Transistor size of pmos greater than nmos in cmos circuits. What is the reason for transistor sizing?
Pmos & Nmos transistors are of same size in Transmission gate. What is the reason?
NAND vs NOR gate implementation. Which is preferred and why?
Velocity saturation?
2ndary effects in Deep sub-micron devices?
CMOS inverter transfer characteristics?
Channel length modulation?
Draw the CMOS implementation of a Boolean equation _______________?
CMOS inverter layout.
How Latchup condition arises in CMOS. How to avoid them?
What is temperature inversion?
What is the difference b/n local skew and global skew?
What is multi-cycle path?
What is false path?