DFT Engineer - Interview Questions 1

Following are the Interview Questions for the Post of DFT Engineer. The questions are collected from my friends, who attended the interviews and Some of them are from the interviews that I've attended.

• What is LSSD and Mux-DFF?
• Draw a logic ciruit to detect a rising edge in an input signal.
• Explain how scan works.
• What are Launch Off Capture,  Launch Off Shift  ?
• What are mealey and moore state machines? advantages and disadvantages.
• Explain boundary scan and tap controller.
• Design rule checks in ATPG (SCAN DRCs)
• Mismatch debug in ATPG.

• What is EDT logic and how does it work?
• How do the chains connect in EDTbypass mode? Compression ratio?
• How does the tester time reduce in EDT?
• Can you put just 1 flop in EDT mode chains and reduce the tester time to just 1 shift??
• Patterns count increases if chain length is reduced. Y??
• What is LOC, LOS? How do they work? Waveforms??
• What is DFT ? what are its adv and disadv?
• Why delay increases if u use mux DFF?
• What happens to setup time of the DFF in Mux DFF??
• Some comb logic is given.. is that fully controllable and observable ??
• Some Sequential ckt..  Controllable and observable ?? what do you do to make it become so??
• Parallel pattern mismatches? How did u debug?
• Lock up latch use?
• Positive and negative edge triggered flops.. how will u connect in a chain?
• JTAG TAP?

• Explain EDT logic. Decompressor, Compactor.
• Masking logic, Mask shift and hold regs.
• Compression ratio, EDT control signals – EDT update, EDT clock
• Fault aliasing, Masking bits generation – coverage effects.
• 2x1 MUX using NAND gates.
• Generate a Clock div by 2, with 25% duty cycle.
• To detect a fault in a circuit, what are the input test vectors to be given?
• All Test Patterns for an 2-input AND gate (optimal set).
• Sequence detector, whole circuit. 
• Setup time, Hold time problems.
• LOC, LOS differences. 
• Scan chain diagnosis – serial pattern failing on Silicon, How do you detect?
• ATPG DRC violations?
• Simulation mismatches debug.  
• JTAG – Instructions – intest, extest, preload/sample.
• LOC, LOS – main difference.
• Scan chain connections, mux-DFF. (How is a scan chain is connected?)