Physical Design Engineer - Interview Questions

Following are the Interview Questions for the Post of Physical Design Engineer. The questions are collected from my friends, who attended the interviews.

Given a circuit, what is the minimum time period of the clock so that the circuit can function properly?

What are the worst case and best case scenarios for timing analysis? (PVT corners)

What are the PVT variations? Why do they occur in the Silicon?

Explain Temperature inversion?

Why do we do timing sign-off at -10 degrees temperature, even though after Power-up, the chip temperature increases above the room temperature? 

What happens immediately after you Power-up the chip?

Difference between a latch and flip-flop?

Draw a flip-flop using two latches. Explain using waveforms.

Why do we use a lock-up latch in DFT ? Explain using waveforms.

Given a circuit, explain how you do setup and hold checks.

If there are any hold violations, what would you do?

IF there are any setup violations, what would you do?

For which case, you consider minimum delays, and for which case, you would consider max delays?

What are the min,typ,max delays specified in a timing library?

What are all the factors that the Cell delay depend on?

If we have setup violations, we do clock-pushing(skewing the capture clock-edge). Would you do clock-pushing for all the flops in your design? (if all flops have setup violations) If no, Why?

Given a ckt., what all data would you need to do STA? 

What info would be there in the Timing libs in STA/synthesis ?

Does the Clock-Q of a flop depends on transition of D input ?

Does the setup time vary for a flop?

A train of length 100m is running a speed of 60KMPH. How much time does it take to pass a platform of length 1KM?

Explain the steps in synthesis in detail.

What is incremental synthesis?

What is the info present in .lib files?

How does the load capacitance and transition time effect the delay?

What if a load cap or trns time exceeds the values in .lib? How does the tool handle it?

What would you do to reduce transition time ? 

Given a circuit, find the maximum operating frequency.

Will hold violation be there if you increase the frequency? Why?

What are the different corners for which you did STA?

Why do you do STA at two corners for slow process? (slow125, slown10)

What is Cbest/worst, RCbest/worst?

How does clock skew effect the timing?

What are on-chip variations? How do you take care of them ?

What is clock uncertainty? 

Given a ckt., tell what delays (min, typ, max) will you consider at different places(data path, clock path) for setup checks, and for hold checks. Why ?

How does an inverter work if the PMOS and NMOS are switched?

Transistor size of pmos greater than nmos in cmos circuits. What is the reason for transistor sizing?

Pmos & Nmos transistors are of same size in Transmission gate. What is the reason?

NAND vs NOR gate implementation. Which is preferred and why?

Velocity saturation?

2ndary effects in Deep sub-micron devices?

CMOS inverter transfer characteristics?

Channel length modulation?

Draw the CMOS implementation of a Boolean equation _______________?

CMOS inverter layout.

How Latchup condition arises in CMOS. How to avoid them?

What is temperature inversion?

What is the difference b/n local skew and global skew?

What is multi-cycle path?

What is false path?