Following are the Interview Questions for the Post of RTL Verification Engineer, at a Top semiconductor product based company in Bengaluru.
I don't remember few questions in the written test. Please don't mind.
WRITTEN TEST - 20 QUESTIONS (8 Digital, 6 Verilog and 6 Aptitude) - 45 MIN.
1. draw a circuit to divide a clock by 2.
2. draw a circuit to multiply a clock with 2.
3. draw a state diagram for sequence detector for 1011
4. draw a logic circuit for Y = X*X where X is a 2 bit input.
5. draw a logic circuit +ve level sensitive latch using 2:1 MUX
6. draw a logic circuit for a -ve edge triggered flipflop using 2:1 MUXes
7. design a mod-5 counter.
8. calculate the max. frequency of operation. (CLK-Q delay, combinational logic delay, setup and hold times are given.)
1. write the verilog code for the state machine above.
2. question on different delay assignment statements in verilog.. draw the waveforms.
3. if(a) if(a=1) if(a==1) if(a===1) .. if a is X, what will be the output. which part of the if-else case is executed?
4. question on parameter, defparameter.. what is a parameter is defined again? overridden?
5. question on execution on blocking and non-blocking statements.
1. 25 horses are there. only 5 can be put in race at once. what is the min. nmbr of races to decide the fastest horse?
2. average of 5 nmbrs starting from m is n. avg of 9 nmbrs starting from m+2 is ?
INTERVIEW QUESTIONS::
ROUND 1:
Explain CMOS inverter operation.
Design all basic gates using 2:1 MUX.
Design a counter which counts a sequence of 1, 3,5 and 7. minimum number of flops required for this?
CMOS inverter has delay of 2ns. An input pulse of width less than 2ns is give. will is pass through the gate?
what is logical effort? explain logical effort calculation for a CMOS inverter and other gates (XOR, XNOR)?
what are asynchronous and synchronous reset? which is better ? why?
design a priority encoder(8x3). where do you use it?
The delay of circuit depends on ? critical path, setup time.
what are adv and disadv of mealey and moore machines?
What is event queue ?
What happens in a CMOS inverter when PMOS and NMOS are interchanged?
In CMOS inverter, vdd=5v, vss=0v, Vthp=vthn=1.8V, input = 1.8v is given. what will be the output?
ROUND 2:
Synchronize the below pulse with the clock and reduce its width to one clock period.
____________
______| |___________ ( here the pulse width is more than 3 clock periods )
Net delay and gate delay assignments in verilog?
Blocking and non-blocking statements and where they are used?
Explain the MOS transistor operation.
Setup time and hold times of a flop and a latch?
CLK-Q delay in a flop and D-Q delay of a latch.
ROUND 3:
12,6,6,3,6,9,18,45, ?? what is the next number?
A question on faces of a dice?
8 balls are there. 1 defective ball is present in them. you have a weighing balance.
using only 2 times , how will you find out the defective ball?
How will you create 4 equilateral triangles using 6 match sticks?
what is the angle between hours and minutes hand at 8:10 ?
draw a ckt to increase the pulse width to 3 periods.
XOR gate is there. output is fedback to 1 input. what will be the output?
A person had 17 cows. How to share them between his 3 sons in fractions of 1/2, 1/3, 1/9th of total respectively. (There is nothing wrong in this question)
I don't remember few questions in the written test. Please don't mind.
WRITTEN TEST - 20 QUESTIONS (8 Digital, 6 Verilog and 6 Aptitude) - 45 MIN.
1. draw a circuit to divide a clock by 2.
2. draw a circuit to multiply a clock with 2.
3. draw a state diagram for sequence detector for 1011
4. draw a logic circuit for Y = X*X where X is a 2 bit input.
5. draw a logic circuit +ve level sensitive latch using 2:1 MUX
6. draw a logic circuit for a -ve edge triggered flipflop using 2:1 MUXes
7. design a mod-5 counter.
8. calculate the max. frequency of operation. (CLK-Q delay, combinational logic delay, setup and hold times are given.)
1. write the verilog code for the state machine above.
2. question on different delay assignment statements in verilog.. draw the waveforms.
3. if(a) if(a=1) if(a==1) if(a===1) .. if a is X, what will be the output. which part of the if-else case is executed?
4. question on parameter, defparameter.. what is a parameter is defined again? overridden?
5. question on execution on blocking and non-blocking statements.
1. 25 horses are there. only 5 can be put in race at once. what is the min. nmbr of races to decide the fastest horse?
2. average of 5 nmbrs starting from m is n. avg of 9 nmbrs starting from m+2 is ?
INTERVIEW QUESTIONS::
ROUND 1:
Explain CMOS inverter operation.
Design all basic gates using 2:1 MUX.
Design a counter which counts a sequence of 1, 3,5 and 7. minimum number of flops required for this?
CMOS inverter has delay of 2ns. An input pulse of width less than 2ns is give. will is pass through the gate?
what is logical effort? explain logical effort calculation for a CMOS inverter and other gates (XOR, XNOR)?
what are asynchronous and synchronous reset? which is better ? why?
design a priority encoder(8x3). where do you use it?
The delay of circuit depends on ? critical path, setup time.
what are adv and disadv of mealey and moore machines?
What is event queue ?
What happens in a CMOS inverter when PMOS and NMOS are interchanged?
In CMOS inverter, vdd=5v, vss=0v, Vthp=vthn=1.8V, input = 1.8v is given. what will be the output?
ROUND 2:
Synchronize the below pulse with the clock and reduce its width to one clock period.
____________
______| |___________ ( here the pulse width is more than 3 clock periods )
Net delay and gate delay assignments in verilog?
Blocking and non-blocking statements and where they are used?
Explain the MOS transistor operation.
Setup time and hold times of a flop and a latch?
CLK-Q delay in a flop and D-Q delay of a latch.
ROUND 3:
12,6,6,3,6,9,18,45, ?? what is the next number?
A question on faces of a dice?
8 balls are there. 1 defective ball is present in them. you have a weighing balance.
using only 2 times , how will you find out the defective ball?
How will you create 4 equilateral triangles using 6 match sticks?
what is the angle between hours and minutes hand at 8:10 ?
draw a ckt to increase the pulse width to 3 periods.
XOR gate is there. output is fedback to 1 input. what will be the output?
A person had 17 cows. How to share them between his 3 sons in fractions of 1/2, 1/3, 1/9th of total respectively. (There is nothing wrong in this question)
Will you put solutions also?
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